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FET BIAS CONTROLLER WITH POLARISATION SWITCH AND TONE DETECTION
ISSUE 1 - JUNE 2001 DEVICE DESCRIPTION
The ZNBG series of devices are designed to meet the bias requirements of GaAs and HEMT FETs commonly used in satellite receiver LNBs, PMR, cellular telephones etc. with a minimum of external components. With the addition of two capacitors and a resistor the devices provide drain voltage and current control for three external grounded source FETs, generating the regulated negative rail required for FET gate biasing whilst operating from a single supply. This negative bias, at -2.8 volts, can also be used to supply other external circuits. The ZNBG3115/16 includes bias circuits to drive up to three external FETs. A control input to the device selects either one of two FETs as operational, the third FET is permanently active. This feature is normally used as an LNB polarisation switch. Also specific to Universal LNB applications is the 22kHz tone detection and logic output feature which is used to enable high and low band frequency switching. The ZNBG3115/16 has been designed to cope with DiSEqCTM ready set top boxes and rejects all transients from channel switching.
ZNBG3115 ZNBG3116
Drain current setting of the ZNBG3115/16 is user selectable over the range 0 to 15mA, this is achieved with addition of a single resistor. The series also offers the choice of drain voltage to be set for the FETs, the 3115 gives 2.2 volts drain whilst the 3116 gives 2 volts. These devices are unconditionally stable over the full working temperature with the FETs in place, subject to the inclusion of the recommended gate and drain capacitors. These ensure RF stability and minimal injected noise. It is possible to use less than the devices full complement of FET bias controls, unused drain and gate connections can be left open circuit without affecting operation of the remaining bias circuits. To protect the external FETs the circuits have been designed to ensure that, under any conditions including power up/down transients, the gate drive from the bias circuits cannot exceed the range -3.5V to 1V. Additionally each stage has its own individual current limiter. Furthermore if the negative rail experiences a fault condition, such as overload or short circuit, the drain supply to the FETs will shut down avoiding excessive current flow. The ZNBG3115/16 are available in QSOP16 and QSOP20 for the minimum in device size. Device operating temperature is -40 to 80C to suit a wide range of environmental conditions.
FEATURES
APPLICATIONS
* * * * * * * * * * * * *
Provides bias for GaAs and HEMT FETs Drives up to three FETs Dynamic FET protection Drain current set by external resistor Regulated negative rail generator requires only 2 external capacitors Choice in drain voltage Wide supply voltage range Polarisation switch for LNBs 22kHz tone detection for band switching Tone detector ignores unwanted signals Support fr MIMIC, FET and Bipolar local oscillator devices Compliant with ASTRA control specifications QSOP 16 and 20 surface mount packages
* * *
Satellite receiver LNBs Private mobile radio (PMR) Cellular telephones
ISSUE 1 - JUNE 2001
1
ZNBG3115 ZNBG3116
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Supply Current Input Voltage (VPOL) Drain Current (per FET) (set by RCAL) Operating Temperature Storage Temperature -0.6V to 12V 100mA 25V Continuous 0 to 15mA -40 to 80C -50 to 85C Power Dissipation (Tamb= 25C) QSOP16 500mW QSOP20 500mW
ELECTRICAL CHARACTERISTICS. TEST CONDITIONS (Unless otherwise stated):Tamb= 25C,VCC=5V,ID=10mA (RCAL=33k )
SYMBOL PARAMETER CONDITIONS MIN. VCC ICC Supply Voltage Supply Current ID1 = ID2 (or ID12) = ID3=0 ID1=0, ID2 (or ID12)=ID3=10mA, VPOL=14V ID2=0,ID1 (or ID12)=ID3=10mA, VPOL=15.5V ID1 and ID3=0, ILB=10mA ID1 and ID3=0, IHB=10mA (Internally generated) ICSUB=0 ICSUB=-200A CG=4.7nF, CD=10nF CG=4.7nF, CD=10nF 180 330 -3.05 5 8.5 28 28 18 18 -2.8 LIMITS TYP. MAX. 10 15 35 35 25 25 -2.55 -2.4 0.02 0.005 800 V mA mA mA mA mA V V Vpkpk Vpkpk kHz UNITS
VSUB
Substrate Voltage Output Noise Drain Voltage Gate Voltage Oscillator Frequency
END ENG fO
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SYMBOL PARAMETER CONDITIONS MIN. LIMITS TYP. MAX. UNITS
GATE CHARACTERISTICS
IGO Output Current Range VPOL IDx (mA) (V) VG1O VG1L VG1H VG2O VG2L VG2H VG3L VG3H Output Voltage Gate 1 Off Low High Output Voltage Gate 2 Off Low High Output Voltage Gate 3 Low High IGOx ( A) -2.5 -2.5 0.4 -2.5 -2.5 0.4 -3.0 0.4 -2.25 -2.25 0.75 -2.25 -2.25 0.75 -2.75 0.75 -2.0 -2.0 1.0 -2.0 -2.0 1.0 -2.5 1.0 V V V V V V V V -30 2000 A
ID1=0 VPOL=14 IGO1=-10 ID1=12 VPOL=15.5 IGO1=-10 ID1=8 VPOL=15.5 IGO1=0 ID2=0 VPOL=15.5 IGO2=-10 ID2=12 VPOL=14 IGO2=-10 ID2=8 VPOL=14 IGO2=0 ID3=12 ID3=8 IGO3=-10 IGO3=0
DRAIN CHARACTERISTICS
ID IDrng DIDV DIDV VD1 Current Current range Current Change with VCC with Tj Set by Rcal VCC= 5 to 10V Tj=-40 to +80C 2.0 1.8 2.0 1.8 2.0 1.8 8 0 0.5 0.05 2.2 2.0 2.2 2.0 2.2 2.0 0.5 50 2.4 2.2 2.4 2.2 2.4 2.2 10 12 15 mA mA %/V %/C V V V V V V %/V ppm
Drain 1 Voltage: High ZNBG3115 ID1=10mA, VPOL=15.5V ZNBG3116 ID1=10mA, VPOL=15.5V Drain 2 Voltage: High ZNBG3115 ID2=10mA, VPOL=14V ZNBG3116 ID2=10mA, VPOL=14V Drain 3 Voltage: High ZNBG3115 ID3=10mA, VPOL=15.5V ZNBG3116 ID3=10mA, VPOL=15.5V Voltage Change with VCC with Tj Leakage Current Drain 1 Drain 2 VCC= 5 to 10V Tj=-40 to +80C
VD2
VD3
VDV VDT IL1 IL2
VD1=0.5V, VPOL=14V VD2=0.5V, VPOL=15.5V
10 10
A A
QSOP20 only
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SYMBOL PARAMETER CONDITIONS MIN. LIMITS TYP. MAX. UNITS
TONE DETECTION CHARACTERISTICS
VOUT Finz AG FVT VLOV ILOV VLBL Filter Amplifier Bias Voltage 5 Input Impedance Amplifier Gain V Threshold5 Output Stage LOV Volt. Range 6 LOV Bias Current LB Output Low IL=50mA(LB or HB) VLOV=0 VLOV=0 IL=0 Rlb-Csub=1M VLOV=3V IL=0mA Rlb-Csub=1M VLBH VHBL LB Output High HB Output Low VLOV=0 IL=10mA VLOV=3V IL=50mA VLOV=0 IL=0 Rhb-Csub=1M VLOV=3V IL=0 Rhb-Gnd=1M VHBH HB Output High VLOV=0 IL=10mA VLOV=3V IL=50mA Enabled Enabled
6
Ifin=0 VFIN=100mV p/p VFIN=100mV p/p
1.75
1.95 150 30
2.15
V V/mA
100 -0.5 0.02 -3.05
6
170
350
mV p/p
VCC-1.8 V 0.15 -2.80 0 1.0 -2.55 0.1 0.025 3.1 -2.55 0.1 0.025 3.1 A V V V V V V V V V A V ms
-0.01
Disabled 6 Disabled 6 Disabled 6
-0.025 0 2.9 3.0 -3.05 -2.80 0
Disabled
6
-0.01 Enabled 6 Enabled 6
-0.025 0 2.9 3.0
POLARITY SWITCH CHARACTERISTICS
IPOL VTPOL TSPOL
NOTES: 1. The negative bias voltages specified are generated on-chip using an internal oscillator. Two external capacitors, CNB and CSUB, of 47nF are required for this purpose. 2. The characteristics are measured using an external reference resistor RCAL of value 33k wired from pins RCAL to ground. 3. Noise voltage is not measured in production. 4. Noise voltage measurement is made with FETs and gate and drain capacitors in place on all outputs. CG, 4.7nF, are connected between gate outputs and ground, CD, 10nF, are connected between drain outputs and ground. 5 . These parameters are linearly related to VCC 6. These parameters are measured using Test Circuit 1
Input Current Threshold Voltage Switching Speed
VPOL=25V (Applied via RPOL=2k) VPOL=25V (Applied via RPOL=2k) VPOL=25V (Applied via RPOL=2k)
10 14
25
40
14.75 15.5 100
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TEST CIRCUIT 1
Note: Same circuit used for QSOP16 option but with adjusted pinout.
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ZNBG3115 ZNBG3116
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ZNBG3115 ZNBG3116
FUNCTIONAL DIAGRAM
FUNCTIONAL DESCRIPTION
The ZNBG devices provide all the bias requirements for external FETs, including the generation of the negative supply required for gate biasing, from the single supply voltage.The diagram above shows a single stage from the ZNBG series. The ZNBG3115/16 contains 3 such stages. The negative rail generator is common to both devices. The drain voltage of the external FET QN is set by the ZNBG device to its normal operating voltage. This is determined by the on board VD Set reference, for the ZNBG3115 this is nominally 2.2 volts whilst the ZNBG3116 provides nominally 2 volts. The drain current taken by the FET is monitored by the low value resistor ID Sense. The amplifier driving the gate of the FET adjusts the gate voltage of QN so that the drain current taken matches the current called for by an external resistor RCAL. Since the FET is a depletion mode transistor, it is often necessary to drive its gate negative with respect to ground to obtain the required drain current. To provide this capability powered from a single positive supply, the device includes a low current negative supply generator. This generator uses an internal oscillator and two external capacitors, CNB and CSUB.
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ZNBG3115 ZNBG3116
The following schematic shows the function of the VPOL input. Only one of the two external FETs numberd Q1 and Q2 are powered at any one time, their selection is controlled by the input VPOL. This input is designed to be wired to the power input of the LNB via a high value (10k) resistor. With the input voltage of the LNB set at or below 14V, FET Q2 will be enabled. With the input voltage at or above 15.5V, FET Q1 will be enabled. The disabled FET has its gate driven low and its drain terminal is switched open circuit. It is permissible to connect the drain pins D1 and D2 together if required by the application circuit; this is done internally in the QSOP16 version. FET number Q3 is always active regardless of the voltage applied to VPOL.
QSOP 20 Version
Control Input Switch Function Input Sense 14 volts 15.5 volts Polarisation Vertical Horizontal Select FET Q2 FET Q1
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ZNBG3115 ZNBG3116
For many LNB applications, tone detection for band switching is required. The ZNBG3115/16 includes all the circuitry necessary to detect the presence of a 22kHz tone modulated on the supply input to the LNB. The main elements of the detector are an op-amp, a rectifier/smoother and a comparitor. The op-amp has a pre-set internal feedback resistor so that just a simple RC network wired to the input gives user defined gain and low frequency cut filter characteristics. The RC network components also serve two other purposes. The resistor provides overvoltage protection for the Vpol pin and the capacitor minimises tone interference of the Vpol threshold. The upper frequency roll-off of the op-amp has been set internally at above 100kHz to allow the amplifier to be used with other common tone switch frequencies. The rectifier/smoother/comparitor function is provided by a complex propriety circuit that allows the ZNBG3115/16 to reliably detect wanted tones whilst ignoring low frequency square wave switch box signals, DiSEqCTM bursts and supply switching transients common when using DiSEqC-2TM ready set-top boxes. This is all achieved without the need for any further external components. The threshold of the comparitor is supply dependent, hence the gain of the preceding op-amp must be adjusted in line with supply voltage. See the table below for recommended values for 22kHz detection, given for a range of supplies.
Table_1 Filter Components Cf Rvpol (R2) Supply Voltage (Vcc) 5V 4.7nF 2k 6V 4.7nF 1.8k 7V 4.7nF 1.5k 8V 10nF 1.3k 9V 10nF 1.1k 10V 10nF 1.0k
Note: Optimised for F(tone) = 22kHz.
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ZNBG3115 ZNBG3116
APPLICATIONS CIRCUIT
The diagrams below show partial application circuits for the ZNBG series showing all external components required for appropriate biasing. The bias circuits are unconditionally stable over the full temperature range with the associated FETs and gate and drain capacitors in circuit. To minimise board space the ZNBG3115/3116 is offered in a QSOP16 package. To reduce the pin count Drain 1 and Drain 2 have been internally connected. This is possible because only one of the two bias stages can biased at one time.The QSOP16 offers a 40% reduction in size over the QSOP20 version. Capacitors C2 and C4 ensure that residual power supply and substrate generator noise is not allowed to affect other external circuits which may be sensitive to RF interference. They also serve to suppress any potential RF feedthrough between stages via the ZNBG device. These capacitors are required for all stages used. Values of 10nF and 4.7nF respectively are recommended however this is design dependent and any value between 1nF and 100nF could be used. The capacitors CNB and CSUB are an integral part of the ZNBGs negative supply generator. The negative bias voltage is generated on-chip using an internal oscillator. The required value of capacitors CNB and CSUB is 47nF. This generator produces a low current supply of approximately -3 volts. Although this generator is intended purely to bias the external FETs, it can be used to power other external circuits via the CSUB pin. Resistor RCAL sets the drain current at which all external FETs are operated. If any bias control circuit is not required, its related drain and gate connections may be left open circuit without af f ecti n g th e o p e ra t i on of t he remaining bias circuits. Th e Z NB G d e v i c e s ha v e be e n designed to protect the external FETs from adverse operating conditions. With a JFET connected to any bias circuit, the gate output voltage of the bias circuit can not exceed the range -3.0V to 1V under any conditions, including powerup and powerdown transients. All the bias stages include drain currents limits which work independently in each stage. Should the negative bias generator be shorted or overloaded so that the drain current of the external FETs can no longer be controlled, the drain supply to FETs is shut down to avoid damage to the FETs by excessive drain current.
QSOP16 Applications circuit
QSOP20 Applications circuit
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ZNBG3115 ZNBG3116
APPLICATIONS INFORMATION(cont)
The following block diagram shows the main section of an LNB designed for use with the Astra series of satellites. The ZNBG3115/16 is the core bias and control element of this circuit. The ZNBG provides the negative rail, FET bias control, polarisation switch control, tone detection and band switching with the minimum of external components. Compared to other discrete component solutions the ZNBG circuit reduces component count and overall size required. Single Universal LNB Block Diagram
Regulator
ZNBG3115/16
Tone detection and band switching is provided on the ZNBG3115/16 devices. The following diagrams describes how this feature operates in an LNB and the external components required. The presence or absence of a 22kHz tone applied to pin FIN enables one of two outputs, LB and HB. A tone present enables HB and tone absent enables LB. The LB and HB outputs are designed to be compatible with both MMIC and discrete (bipolar or FET) local oscillator applications, selected by pin LOV. Referring to Figure 1 wiring pin LOV to ground will force LB and HB to switch between -2.6V (disabled) and 0V (enabled). Referring to Figures 2 and 3 wiring pin LOV to a positive voltage source (e.g. a potential divider across VCC and ground set to the required oscillator supply voltage, VOSC) will force the LB and HB outputs to provide the required oscillator supply, VOSC, when enabled and 0V when disabled. Tone Detection Function LOV GND FIN 22kHz -- VOSC 22kHz -- Note 1: LB Disabled Enabled Disabled Enabled HB Enabled Disabled Enabled Disabled LB -3 volts GND Note 1 VOSC HB GND -3 volts VOSC Note 1
0 volts in typical LNB applications but ependent on extenal circuits.
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ZNBG3115 ZNBG3116
APPLICATIONS Local Oscillator Circuits
Figure 1
Figure 2
Figure 3
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ZNBG3115 ZNBG3116
CONNECTION DIAGRAM
QSOP20 QSOP16
1 2 3 4 5 6 7 8
G1
D1
20 19 18 17 16 15 14 13 12 11
VCC
G1
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC
RCAL VPOL FIN N/C N/C Lov HB LB CSUB
D12 G2 G3 D3 Gnd Cnb1 Cnb2
Rcal Vpol Fin Lov HB LB Csub
G2 D2 G3 D3 GND CNB1 CNB2 N/C
9 10
Part Number ZNBG3115Q16 ZNBG3116Q16 ZNBG3115Q20 ZNBG3116Q20
Package QSOP16 QSOP16 QSOP20 QSOP20
Part Mark ZNBG3115 ZNBG3116 ZNBG3115 ZNBG3116
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ZNBG3115 ZNBG3116
QSOP16
DIM Millimetres MIN A B C D E F G J K 4.80 0.635 0.23 REF 0.20 3.81 1.35 0.10 5.79 0 0.30 3.99 1.75 0.25 6.20 8 MAX 4.98 Inches MIN 0.189 MAX 0.196
QSOP20
DIM Millimetres MIN A B C 0.012 0.157 0.069 0.01 0.244 8 D E F G J K 8.55 0.635 1.47 REF 0.20 3.81 1.35 0.10 5.79 0 0.30 3.99 1.75 0.25 6.20 8 MAX 8.74 Inches MIN 0.337 MAX 0.344
0.025 NOM 0.009 REF 0.008 0.15 0.053 0.004 0.228 0
0.025 NOM 0.058 REF 0.008 0.15 0.053 0.004 0.228 0 0.012 0.157 0.069 0.01 0.244 8
Conforms to JEDEC MO-137AB Iss A
Conforms to JEDEC MO-137AD Iss A
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